A defect-tolerant systolic array implementation for real time image processing

Publikation: Beitrag in FachzeitschriftArtikelForschungPeer-Review

Autoren

  • V. Hecht
  • K. Rönner
  • P. Pirsch
Forschungs-netzwerk anzeigen

Details

OriginalspracheEnglisch
Seiten (von - bis)37-47
Seitenumfang11
FachzeitschriftJournal of VLSI Signal Processing
Jahrgang5
Ausgabenummer1
PublikationsstatusVeröffentlicht - 1 Jan. 1993

Abstract

An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real time image processing applications has been full-custom designed and fabricated using standard CMOS technology. The bit-serial systolic array incorporates new architectural concepts and circuit techniques fitting a defect tolerant design approach. Therefore high performance and high yield enhancement is achieved. The defect tolerance techniques are based on software controlled defect localization and reconfiguration with programmable switches by a host-processor or a VLSI-tester. The chips functionality differs to available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip line delays and implemented special processing of frames borders. High performance implementations of signal processing algorithms require large chip die sizes. The presented defect tolerance techniques and architectural concepts make systolic large area implementations of signal processing algorithms feasible.

ASJC Scopus Sachgebiete

Zitieren

A defect-tolerant systolic array implementation for real time image processing. / Hecht, V.; Rönner, K.; Pirsch, P.
in: Journal of VLSI Signal Processing, Jahrgang 5, Nr. 1, 01.01.1993, S. 37-47.

Publikation: Beitrag in FachzeitschriftArtikelForschungPeer-Review

Hecht V, Rönner K, Pirsch P. A defect-tolerant systolic array implementation for real time image processing. Journal of VLSI Signal Processing. 1993 Jan 1;5(1):37-47. doi: 10.1007/BF01880270
Hecht, V. ; Rönner, K. ; Pirsch, P. / A defect-tolerant systolic array implementation for real time image processing. in: Journal of VLSI Signal Processing. 1993 ; Jahrgang 5, Nr. 1. S. 37-47.
Download
@article{19f79cd1d42e4cf7977d2b46cbf00bb4,
title = "A defect-tolerant systolic array implementation for real time image processing",
abstract = "An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real time image processing applications has been full-custom designed and fabricated using standard CMOS technology. The bit-serial systolic array incorporates new architectural concepts and circuit techniques fitting a defect tolerant design approach. Therefore high performance and high yield enhancement is achieved. The defect tolerance techniques are based on software controlled defect localization and reconfiguration with programmable switches by a host-processor or a VLSI-tester. The chips functionality differs to available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip line delays and implemented special processing of frames borders. High performance implementations of signal processing algorithms require large chip die sizes. The presented defect tolerance techniques and architectural concepts make systolic large area implementations of signal processing algorithms feasible.",
author = "V. Hecht and K. R{\"o}nner and P. Pirsch",
year = "1993",
month = jan,
day = "1",
doi = "10.1007/BF01880270",
language = "English",
volume = "5",
pages = "37--47",
journal = "Journal of VLSI Signal Processing",
issn = "0922-5773",
publisher = "Springer New York",
number = "1",

}

Download

TY - JOUR

T1 - A defect-tolerant systolic array implementation for real time image processing

AU - Hecht, V.

AU - Rönner, K.

AU - Pirsch, P.

PY - 1993/1/1

Y1 - 1993/1/1

N2 - An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real time image processing applications has been full-custom designed and fabricated using standard CMOS technology. The bit-serial systolic array incorporates new architectural concepts and circuit techniques fitting a defect tolerant design approach. Therefore high performance and high yield enhancement is achieved. The defect tolerance techniques are based on software controlled defect localization and reconfiguration with programmable switches by a host-processor or a VLSI-tester. The chips functionality differs to available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip line delays and implemented special processing of frames borders. High performance implementations of signal processing algorithms require large chip die sizes. The presented defect tolerance techniques and architectural concepts make systolic large area implementations of signal processing algorithms feasible.

AB - An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real time image processing applications has been full-custom designed and fabricated using standard CMOS technology. The bit-serial systolic array incorporates new architectural concepts and circuit techniques fitting a defect tolerant design approach. Therefore high performance and high yield enhancement is achieved. The defect tolerance techniques are based on software controlled defect localization and reconfiguration with programmable switches by a host-processor or a VLSI-tester. The chips functionality differs to available convolution chips by the maximum kernel size of 256 taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip line delays and implemented special processing of frames borders. High performance implementations of signal processing algorithms require large chip die sizes. The presented defect tolerance techniques and architectural concepts make systolic large area implementations of signal processing algorithms feasible.

UR - http://www.scopus.com/inward/record.url?scp=0027311507&partnerID=8YFLogxK

U2 - 10.1007/BF01880270

DO - 10.1007/BF01880270

M3 - Article

AN - SCOPUS:0027311507

VL - 5

SP - 37

EP - 47

JO - Journal of VLSI Signal Processing

JF - Journal of VLSI Signal Processing

SN - 0922-5773

IS - 1

ER -