A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

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OriginalspracheEnglisch
Titel des SammelwerksISCAS 2024 - IEEE International Symposium on Circuits and Systems
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
Seitenumfang5
ISBN (elektronisch)9798350330991
ISBN (Print)979-8-3503-3100-4
PublikationsstatusVeröffentlicht - 2024
Veranstaltung2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - , Singapur
Dauer: 19 Mai 202422 Mai 2024

Publikationsreihe

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Abstract

This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.

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A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. / Flemming, Jesko; Wicht, Bernhard; Witte, Pascal.
ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2024. (Proceedings - IEEE International Symposium on Circuits and Systems).

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

Flemming, J, Wicht, B & Witte, P 2024, A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. in ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapur, 19 Mai 2024. https://doi.org/10.1109/ISCAS58744.2024.10557987
Flemming, J., Wicht, B., & Witte, P. (2024). A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. In ISCAS 2024 - IEEE International Symposium on Circuits and Systems (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS58744.2024.10557987
Flemming J, Wicht B, Witte P. A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. in ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2024. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS58744.2024.10557987
Flemming, Jesko ; Wicht, Bernhard ; Witte, Pascal. / A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2024. (Proceedings - IEEE International Symposium on Circuits and Systems).
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title = "A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs",
abstract = "This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.",
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AU - Flemming, Jesko

AU - Wicht, Bernhard

AU - Witte, Pascal

N1 - Publisher Copyright: © 2024 IEEE.

PY - 2024

Y1 - 2024

N2 - This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.

AB - This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.

KW - analog-to-digital converter

KW - hardware-sharing

KW - incremental delta-sigma modulator

KW - linearization

KW - time-interleaved

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U2 - 10.1109/ISCAS58744.2024.10557987

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024

Y2 - 19 May 2024 through 22 May 2024

ER -

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