Details
| Originalsprache | Englisch |
|---|---|
| Seiten | 126-129 |
| Seitenumfang | 4 |
| Publikationsstatus | Veröffentlicht - 2018 |
Abstract
The level shifter and the floating gate supply for high-side transistors are a major challenge in high-voltage DCDC converters. This paper presents a high-speed and power-efficient level shifter for voltages of up to 50 V, suitable for both PMOS and NMOS power FETs. A switching node falling edge detection allows both, a sensitive and safe signal detection. This enables a robust operation during steep dv/dt transitions and a power consumption as low as 4.1 pJ per switching cycle, which is a reduction of more than 40 % compared to prior art. An active clamping circuit prevents common mode displacement currents into the high-side supply. The level shifter is implemented in a 180 nm BiCMOS technology. Measurements confirm a 50 V 120 MHz high-speed operation of the level shifter with a rising/falling propagation delay of 1.45 ns/1.3 ns, respectively. The dv/dt robustness has been confirmed by measurements for transitions up to 6 V/ns.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
- Physik und Astronomie (insg.)
- Instrumentierung
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2018. 126-129.
Publikation: Konferenzbeitrag › Paper › Forschung › Peer-Review
}
TY - CONF
T1 - A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters.
AU - Lutz, Daniel
AU - Seidel, Achim
AU - Wicht, Bernhard
N1 - Publisher Copyright: © 2018 IEEE.
PY - 2018
Y1 - 2018
N2 - The level shifter and the floating gate supply for high-side transistors are a major challenge in high-voltage DCDC converters. This paper presents a high-speed and power-efficient level shifter for voltages of up to 50 V, suitable for both PMOS and NMOS power FETs. A switching node falling edge detection allows both, a sensitive and safe signal detection. This enables a robust operation during steep dv/dt transitions and a power consumption as low as 4.1 pJ per switching cycle, which is a reduction of more than 40 % compared to prior art. An active clamping circuit prevents common mode displacement currents into the high-side supply. The level shifter is implemented in a 180 nm BiCMOS technology. Measurements confirm a 50 V 120 MHz high-speed operation of the level shifter with a rising/falling propagation delay of 1.45 ns/1.3 ns, respectively. The dv/dt robustness has been confirmed by measurements for transitions up to 6 V/ns.
AB - The level shifter and the floating gate supply for high-side transistors are a major challenge in high-voltage DCDC converters. This paper presents a high-speed and power-efficient level shifter for voltages of up to 50 V, suitable for both PMOS and NMOS power FETs. A switching node falling edge detection allows both, a sensitive and safe signal detection. This enables a robust operation during steep dv/dt transitions and a power consumption as low as 4.1 pJ per switching cycle, which is a reduction of more than 40 % compared to prior art. An active clamping circuit prevents common mode displacement currents into the high-side supply. The level shifter is implemented in a 180 nm BiCMOS technology. Measurements confirm a 50 V 120 MHz high-speed operation of the level shifter with a rising/falling propagation delay of 1.45 ns/1.3 ns, respectively. The dv/dt robustness has been confirmed by measurements for transitions up to 6 V/ns.
KW - DCDC power converter
KW - high-speed
KW - high-voltage level shifter
KW - low power
UR - http://www.scopus.com/inward/record.url?scp=85056800205&partnerID=8YFLogxK
U2 - 10.1109/esscirc.2018.8494292
DO - 10.1109/esscirc.2018.8494292
M3 - Paper
SP - 126
EP - 129
ER -