Details
| Originalsprache | Englisch |
|---|---|
| Aufsatznummer | 1471106 |
| Seiten (von - bis) | 102-105 |
| Seitenumfang | 4 |
| Fachzeitschrift | European Solid-State Circuits Conference |
| Publikationsstatus | Veröffentlicht - 1999 |
| Veranstaltung | 25th European Solid-State Circuits Conference, ESSCIRC 1999 - Duisburg, Deutschland Dauer: 21 Sept. 1999 → 23 Sept. 1999 |
Abstract
In this paper, a programmable DSP for real time image processing is presented that combines the concepts of VLIW and SIMD with a high utilization of parallel resources on instruction level and data level. The SIMD approach has been extended with autonomous instruction selection capabilities (ASIMD), which offers to control four parallel datapaths with low area overhead. The memory concept is adapted to image processing requirements and follows two basic rules: Shared data have to be accessed regularly in shape of a matrix and are stored in the Matrix Memory. As soon as data are accessed irregularly, they are stored in the private cache memories. The Matrix Memory allows parallel, conflict-free access from all datapaths in a single clock cycle. A first prototype of the DSP with four datapaths achieves 1.3 GOPS performance at 66 MHz, using a 0.5μm CMOS technology.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Hardware und Architektur
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: European Solid-State Circuits Conference, 1999, S. 102-105.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - A 1.3 GOPS parallel DSP for high performance image processing applications
AU - Hinrichs, W.
AU - Wittenburg, J. P.
AU - Lieske, H.
AU - Kloos, H.
AU - Ohmacht, M.
AU - Kneip, J.
AU - Rönner, K.
AU - Pirsch, P.
PY - 1999
Y1 - 1999
N2 - In this paper, a programmable DSP for real time image processing is presented that combines the concepts of VLIW and SIMD with a high utilization of parallel resources on instruction level and data level. The SIMD approach has been extended with autonomous instruction selection capabilities (ASIMD), which offers to control four parallel datapaths with low area overhead. The memory concept is adapted to image processing requirements and follows two basic rules: Shared data have to be accessed regularly in shape of a matrix and are stored in the Matrix Memory. As soon as data are accessed irregularly, they are stored in the private cache memories. The Matrix Memory allows parallel, conflict-free access from all datapaths in a single clock cycle. A first prototype of the DSP with four datapaths achieves 1.3 GOPS performance at 66 MHz, using a 0.5μm CMOS technology.
AB - In this paper, a programmable DSP for real time image processing is presented that combines the concepts of VLIW and SIMD with a high utilization of parallel resources on instruction level and data level. The SIMD approach has been extended with autonomous instruction selection capabilities (ASIMD), which offers to control four parallel datapaths with low area overhead. The memory concept is adapted to image processing requirements and follows two basic rules: Shared data have to be accessed regularly in shape of a matrix and are stored in the Matrix Memory. As soon as data are accessed irregularly, they are stored in the private cache memories. The Matrix Memory allows parallel, conflict-free access from all datapaths in a single clock cycle. A first prototype of the DSP with four datapaths achieves 1.3 GOPS performance at 66 MHz, using a 0.5μm CMOS technology.
UR - http://www.scopus.com/inward/record.url?scp=84893729802&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:84893729802
SP - 102
EP - 105
JO - European Solid-State Circuits Conference
JF - European Solid-State Circuits Conference
SN - 1930-8833
M1 - 1471106
T2 - 25th European Solid-State Circuits Conference, ESSCIRC 1999
Y2 - 21 September 1999 through 23 September 1999
ER -