Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference |
| Herausgeber/-innen | Franz Dielacher, Wolfgang Pribyl, Gernot Hueber |
| Seiten | 184-187 |
| Seitenumfang | 4 |
| ISBN (elektronisch) | 9781467374705 |
| Publikationsstatus | Veröffentlicht - 30 Okt. 2015 |
| Extern publiziert | Ja |
| Veranstaltung | 41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Österreich Dauer: 14 Sept. 2015 → 18 Sept. 2015 |
Publikationsreihe
| Name | European Solid-State Circuits Conference |
|---|---|
| Band | 2015-October |
| ISSN (Print) | 1930-8833 |
Abstract
This paper presents an integrated synchronous buck converter for input voltages >12V with 10MHz switching frequency. The converter comprises a predictive dead time control with frequency compensated sampling of the switching node which does not require body diode forward conduction. A high dead time resolution of 125ps is achieved by a differential delay chain with 8-bit resolution. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching at turn off. The converter was implemented in a 180nm high-voltage BiCMOS technology. The power losses were measured to be reduced by 30% by the proposed dead time control, which results in a 6% efficiency increase at VOUT = 5V and 0.2 A load. The peak efficiency is 81%.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Hardware und Architektur
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference. Hrsg. / Franz Dielacher; Wolfgang Pribyl; Gernot Hueber. 2015. S. 184-187 7313859 (European Solid-State Circuits Conference; Band 2015-October).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - A 12V 10MHz buck converter with dead time control based on a 125 ps differential delay chain
AU - Wittmann, Juergen
AU - Barner, Alexander
AU - Rosahl, Thoralf
AU - Wicht, Bernhard
N1 - Publisher Copyright: © 2015 IEEE.
PY - 2015/10/30
Y1 - 2015/10/30
N2 - This paper presents an integrated synchronous buck converter for input voltages >12V with 10MHz switching frequency. The converter comprises a predictive dead time control with frequency compensated sampling of the switching node which does not require body diode forward conduction. A high dead time resolution of 125ps is achieved by a differential delay chain with 8-bit resolution. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching at turn off. The converter was implemented in a 180nm high-voltage BiCMOS technology. The power losses were measured to be reduced by 30% by the proposed dead time control, which results in a 6% efficiency increase at VOUT = 5V and 0.2 A load. The peak efficiency is 81%.
AB - This paper presents an integrated synchronous buck converter for input voltages >12V with 10MHz switching frequency. The converter comprises a predictive dead time control with frequency compensated sampling of the switching node which does not require body diode forward conduction. A high dead time resolution of 125ps is achieved by a differential delay chain with 8-bit resolution. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching at turn off. The converter was implemented in a 180nm high-voltage BiCMOS technology. The power losses were measured to be reduced by 30% by the proposed dead time control, which results in a 6% efficiency increase at VOUT = 5V and 0.2 A load. The peak efficiency is 81%.
UR - http://www.scopus.com/inward/record.url?scp=84958741152&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2015.7313859
DO - 10.1109/ESSCIRC.2015.7313859
M3 - Conference contribution
AN - SCOPUS:84958741152
T3 - European Solid-State Circuits Conference
SP - 184
EP - 187
BT - ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference
A2 - Dielacher, Franz
A2 - Pribyl, Wolfgang
A2 - Hueber, Gernot
T2 - 41st European Solid-State Circuits Conference, ESSCIRC 2015
Y2 - 14 September 2015 through 18 September 2015
ER -