TY - JOUR

T1 - 3D GaN nanoarchitecture for field-effect transistors

AU - Fatahilah, Muhammad Fahlesa

AU - Strempel, Klaas

AU - Yu, Feng

AU - Vodapally, Sindhuri

AU - Waag, Andreas

AU - Wasisto, Hutomo Suryo

N1 - Funding information: This work has been performed within the projects of ‘LENA-OptoSense’ funded by the Lower Saxony Ministry for Science and Culture (MWK) Landesmittel des Niedersächsischen Vorab and ‘3D Concepts for Gallium-Nitride Electronics (3D GaN)’ funded by the German Research Foundation (DFG). The authors thank Friedhard Römer and Bernd Witzigmann from the University of Kassel, Germany for simulation of the GaN nanowire devices and constructive discussion on the topic of 3D GaN electronics. We also acknowledge the support from the Indonesian-German Center for Nano and Quantum Technologies (IG-Nano) and the Ministry of Research, Technology and Higher Education of the Republic of Indonesia (RISTEKDIKTI) .

PY - 2019/5

Y1 - 2019/5

N2 - The three-dimensionality of 3D GaN field-effect transistors (FETs) provides them with unique advantages compared to their planar counterparts, introducing a promising path towards future FETs beyond Moore's law. Similar to today's Si processor technology, 3D GaN FETs offer multi-gate structures that provide excellent electrostatic control over the channel and enable very low subthreshold swing values close to the theoretical limit. Various concepts have been demonstrated, including both lateral and vertical devices with GaN nanowire (NW) or nanofin (NF) geometries. Outstanding transport properties were achieved with laterally contacted NWs that were grown in a bottom-up approach and transferred onto an insulating substrate. For higher power application, vertical FETs based on regular arrays of GaN nanostructures are particularly promising due to their parallel integration capability and large sidewall surfaces, which can be utilized as channel area. In this paper, we review the current status of 3D GaN FETs and discuss their concepts, fabrication techniques, and performances. In addition to the potential benefits, reliability issues and difficulties that may arise in complex 3D processing are discussed, which need to be tackled to pave the way for future switching applications.

AB - The three-dimensionality of 3D GaN field-effect transistors (FETs) provides them with unique advantages compared to their planar counterparts, introducing a promising path towards future FETs beyond Moore's law. Similar to today's Si processor technology, 3D GaN FETs offer multi-gate structures that provide excellent electrostatic control over the channel and enable very low subthreshold swing values close to the theoretical limit. Various concepts have been demonstrated, including both lateral and vertical devices with GaN nanowire (NW) or nanofin (NF) geometries. Outstanding transport properties were achieved with laterally contacted NWs that were grown in a bottom-up approach and transferred onto an insulating substrate. For higher power application, vertical FETs based on regular arrays of GaN nanostructures are particularly promising due to their parallel integration capability and large sidewall surfaces, which can be utilized as channel area. In this paper, we review the current status of 3D GaN FETs and discuss their concepts, fabrication techniques, and performances. In addition to the potential benefits, reliability issues and difficulties that may arise in complex 3D processing are discussed, which need to be tackled to pave the way for future switching applications.

KW - 3D architecture

KW - Field-effect transistor (FET)

KW - GaN

KW - Lateral transistor

KW - Nanoelectronics

KW - Nanofin

KW - Nanowire

KW - Vertical transistor

UR - http://www.scopus.com/inward/record.url?scp=85064979050&partnerID=8YFLogxK

U2 - 10.1016/j.mne.2019.04.001

DO - 10.1016/j.mne.2019.04.001

M3 - Article

AN - SCOPUS:85064979050

VL - 3

SP - 59

EP - 81

JO - Micro and Nano Engineering

JF - Micro and Nano Engineering

ER -