Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 946-952 |
| Seitenumfang | 7 |
| Fachzeitschrift | IEEE Journal of Solid-State Circuits |
| Jahrgang | 35 |
| Ausgabenummer | 7 |
| Publikationsstatus | Veröffentlicht - Juli 2000 |
Abstract
A programmable digital signal processor (DSP) for real-time image processing is presented that combines the concepts of single-instruction multiple-data (SIMD) and very long instruction word with a high utilization of parallel resources on instruction and data level. The SIMD approach has been extended with autonomous instruction selection capabilities (ASIMD), which offers to control four parallel datapaths with low area overhead. The memory concept is adapted to image-processing requirements and follows two basic rules: shared data have to be accessed regularly in the shape of a matrix and are stored in the matrix memory. As soon as data are accessed irregularly, they are stored in the private cache memories. The matrix memory allows parallel, conflict-free access from all datapaths in a single clock cycle. The DSP achieves 1.3-GOPS performance at 66 MHz. A first prototype in 0.5-μm CMOS technology has been fabricated.
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in: IEEE Journal of Solid-State Circuits, Jahrgang 35, Nr. 7, 07.2000, S. 946-952.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - 1.3-GOPS parallel DSP for high-performance image-processing applications
AU - Hinrichs, Willm
AU - Wittenburg, Jens Peter
AU - Lieske, Hanno
AU - Kloos, Helge
AU - Ohmacht, Martin
AU - Pirsch, Peter
N1 - Funding Information: Manuscript received December 20, 1999; revised February 7, 2000. This work was supported by BWB, Germany. The authors are with the Laboratorium für Informationstechnologie, Univer-sität Hannover, Hannover 30167 Germany. Publisher Item Identifier S 0018-9200(00)03879-8.
PY - 2000/7
Y1 - 2000/7
N2 - A programmable digital signal processor (DSP) for real-time image processing is presented that combines the concepts of single-instruction multiple-data (SIMD) and very long instruction word with a high utilization of parallel resources on instruction and data level. The SIMD approach has been extended with autonomous instruction selection capabilities (ASIMD), which offers to control four parallel datapaths with low area overhead. The memory concept is adapted to image-processing requirements and follows two basic rules: shared data have to be accessed regularly in the shape of a matrix and are stored in the matrix memory. As soon as data are accessed irregularly, they are stored in the private cache memories. The matrix memory allows parallel, conflict-free access from all datapaths in a single clock cycle. The DSP achieves 1.3-GOPS performance at 66 MHz. A first prototype in 0.5-μm CMOS technology has been fabricated.
AB - A programmable digital signal processor (DSP) for real-time image processing is presented that combines the concepts of single-instruction multiple-data (SIMD) and very long instruction word with a high utilization of parallel resources on instruction and data level. The SIMD approach has been extended with autonomous instruction selection capabilities (ASIMD), which offers to control four parallel datapaths with low area overhead. The memory concept is adapted to image-processing requirements and follows two basic rules: shared data have to be accessed regularly in the shape of a matrix and are stored in the matrix memory. As soon as data are accessed irregularly, they are stored in the private cache memories. The matrix memory allows parallel, conflict-free access from all datapaths in a single clock cycle. The DSP achieves 1.3-GOPS performance at 66 MHz. A first prototype in 0.5-μm CMOS technology has been fabricated.
UR - http://www.scopus.com/inward/record.url?scp=0034225390&partnerID=8YFLogxK
U2 - 10.1109/4.848202
DO - 10.1109/4.848202
M3 - Article
AN - SCOPUS:0034225390
VL - 35
SP - 946
EP - 952
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 7
ER -